This application relies from priority upon Korean Patent Application No. 2001-034188, filed on Jun. 16, 2001, the contents of which are herein incorporated by reference in their entirety.
The present invention is related to nonvolatile storage devices. In particular, the present invention is related to a NAND-type flash memory device that is capable of preventing program disturbance due to bouncing of a substrate voltage occurring during a bit line setup period.
Recently, there has been increased a need for memory devices that are capable of being electrically erased and programmed without refreshing stored data. The trend is to increase capacity and integration of memory devices. A NAND-type flash memory device provides large capacity and high integration without refresh for stored data. Since the NAND-type flash memory device maintains data even at power-off, it has been applied widely to electronic equipments (e.g., handheld terminals, portable computers, etc.) where power may be suddenly interrupted.
A nonvolatile semiconductor memory device such as a NAND-type flash memory device includes electrically erasable programmable read-only memory cells, which are named xe2x80x9cflash EEPROM cellsxe2x80x9d. Typically a flash EEPROM cell includes a cell transistor or a floating gate transistor. The transistor is formed in or on a pocket p-type well as a substrate and has n-type source and drain spaced apart from each other, a floating gate placed over a channel between the source and the drain and storing charges, and a control gate placed over the floating gate.
An array structure of a well-known NAND-type flash memory device is shown in FIG. 1. Referring to FIG. 1, a memory cell array is formed in or on a pocket p-type well PPWELL, and includes a plurality of cell strings 10 each corresponding to bit lines. The pocket p-type well PPWELL is formed in an n-type well NWELL that is formed on or in a p-type semiconductor substrate. For convenience, two bit lines BL0 and BL1 and two cell strings 10 corresponding thereto are illustrated in FIG. 1. Each cell string 10 includes a string select transistor SST as a first select transistor, a ground select transistor GST as a second select transistor, and a plurality of flash EEPROM cells MCm (m=0-15) serially connected between the string select transistor SST and the ground select transistor GST. The string select transistor SST has its drain connected to a corresponding bit line and its gate connected to a string select line SSL, and the ground select transistor GST has its source connected to a common source line CSL and its gate connected to a ground select line GSL. The flash EEPROM cells MC15 to MC0 are connected in series between a source of the string select transistor SST and a drain of the ground select transistor GST, and are respectively connected to corresponding word lines WL15 to WL0.
Before programming, all flash EEPROM cells in a memory cell array are simultaneously erased so as to have a threshold voltage of, for example, about xe2x88x923V. And then, in order to program flash EEPROM cells, a program voltage Vpgm is applied to a selected word line and a pass voltage Vpass is applied respectively to unselected word lines. A threshold voltage of a cell connected to the selected word line is increased while threshold voltages of cells connected to the respective unselected word lines are not changed.
One problem arises when programming flash EEPROM cells to be programmed connected to the selected word line without programming flash EEPROM cells to be program inhibited connected to the selected word line. When the program voltage Vpgm is applied to the selected word line, it is applied both to flash EEPROM cells to be programmed and to flash EEPROM cells to be program inhibited. At this time, among the flash EEPROM cells to be program inhibited, connected to the selected word line, in particular, one or more flash EEPROM cells adjacent one to be programmed are inadvertently and undesirably programmed. This is called the xe2x80x9cprogram disturbxe2x80x9d phenomenon.
One technique for preventing the program disturb is a program inhibit method using a self-boosting scheme. The program inhibit method using the self-boosting scheme is disclosed in U.S. Pat. Nos. 5,677,873 and 5,991,202 respectively entitled xe2x80x9cMethod Of Programming Flash EEPROM Integrated Circuit Memory Devices To Prevent Inadvertent Programming Of Nondesignated And Memory Cells Thereinxe2x80x9d and xe2x80x9cMethod For Reducing Program Disturb During Self-boosting In A NAND Flash Memoryxe2x80x9d, the disclosures of which are hereby incorporated by this reference.
A program inhibiting method using the self-boosting scheme is performed as follows. A ground voltage (e.g., 0V) is applied to a gate of the ground select transistor GST so as to shut off a ground path. A selected bit line (e.g., BL0) is supplied with the ground voltage, and an unselected bit line (e.g., BL1) is supplied with a power supply voltage VCC (e.g., 3.3V or 5V). Simultaneously, the power supply voltage VCC is supplied to a gate of the string select transistor SST, so that a source of the string select transistor SST (or a channel of a cell transistor to be program inhibited) is charged up to VCC-Vth (Vth is a threshold voltage of SST). At this time, the string select transistor SST is shut off. A period in which the above-described operations are performed is called xe2x80x9ca bit line setup periodxe2x80x9d.
Next, a program voltage Vpgm is applied to the selected word line and a pass voltage Vpass is applied to the respective unselected word lines, so that a channel voltage of a cell transistor to be program inhibited is boosted. The channel voltage of the cell transistor to be program inhibited, for example, is boosted up to about 8V. This causes no F-N tunneling arise to between a floating gate and a channel of the cell transistor to be program inhibited. Thus, a cell transistor to be program inhibited remains at an initial erased state. A period in which above-described operations are performed is called xe2x80x9ca program periodxe2x80x9d. If a program operation for a selected memory cell is completed, a discharge operation is carried out to discharge voltages on bit lines. The pocket p-type well PPWELL and the n-type well NWELL are grounded during the bit line setup, program and discharge periods.
With the above-described program method, a flash EEPROM cell to be program inhibited, which is adjacent to a flash EEPROM cell to be programmed, suffers from the program disturb phenomenon due to a leakage current flowing through a parasitic field transistor (or a parasitic MOS transistor) as shown in FIG. 1. This will be more fully described below.
Referring to FIG. 2, which is a cross sectional view of an array structure taken along a dotted line A-Axe2x80x2 in FIG. 1, flash EEPROM cells connected to the same word line (e.g., WL14) are electrically isolated from each other by field regions or field oxide regions 12 formed on a pocket p-type well PPWELL. In this structure, adjacent flash EEPROM cells, a word line WL14, and a pocket p-type well PPWELL collectively form a parasitic field or MOS transistor. A channel region of a cell to be program inhibited of the adjacent flash EEPROM cells acts as a drain of the parasitic field transistor, a channel region of a cell to be programmed thereof acts as a source thereof, and the word line WL14 acts as a gate thereof. The pocket p-type well PPWELL close to the field region 12 between a drain and a source of the parasitic field transistor acts as a channel of the parasitic field transistor.
In a case where the program voltage Vpgm applied to the word line WL14 is higher than a threshold voltage of a parasitic field transistor (or a threshold voltage of the parasitic field transistor is lowered), the parasitic field transistor is turned on. This causes a leakage current to flow from a channel region of a cell to be program inhibited to a cell to be programmed through the turned-on parasitic MOS transistor. Since a self-boosted channel voltage of a cell to be program inhibited is lowered, the cell to be program inhibited suffers from the program disturb phenomenon.
There are various causes for the lowering of a threshold voltage of a parasitic field transistor. One is that a voltage of a pocket p-type well PPWELL is bounced from 0V to a positive voltage when charging one or more bit lines with the power supply voltage VCC in a bit line setup period. A pocket p-type well voltage is increased through a coupling capacitor between a bit line and the pocket p-type well. For example, the coupling capacitor exists between a drain of a string select transistor contacted with a bit line and a pocket p-type well. And, the coupling capacitor exists between a bit line and a pocket p-type well. As the integration of a memory device increases, a well voltage may be increased more and more. This is because the number of bit lines simultaneously charged up to the power supply voltage VCC is increased.
In order to prevent the program disturb due to a leakage current flowing through the parasitic field or MOS transistor, after bit lines are charged with the power supply voltage VCC and a time elapses, word line voltages such as the program and pass voltages Vpgm and Vpass are applied to corresponding word lines. That is, after a pocket p-type well voltage VPPWELL is lowered sufficiently, the program and pass voltages are supplied to corresponding word lines. In case that a word line voltage is supplied to a word line at a state that the pocket p-type well voltage VPPWELL is not lowered sufficiently, as illustrated in FIG. 3, a channel voltage of a cell to be program inhibited is not boosted up to a required voltage (a voltage indicated by a dotted line in a figure). That is, a channel voltage is dropped by DV. A point of time when a word line voltage VWL, as shown in FIG. 4, is applied to a word line has to be delayed such that a channel voltage is sufficiently boosted up to a required voltage.
As a point of time when a word line voltage VWL is applied to a word line, a word line enable point of time is t1 in FIG. 4, at which an increased well voltage VPPWELL goes to 0V. A desirable delay time of the word line enable point of time is DtA (e.g., about 2 ms). However, since a stabilized point of time t1 of a well voltage VPPWELL is different in each memory device, it is impossible to forecast the point of time t1 exactly. For this reason, a sufficient margin DtB has to be secured between a bit line enable point of time t0 and a word line enable point of time t2. Accordingly, a total program time increases.
Increase of a program time due to a delay time of a word line enable point of time can be shortened by suppressing the bouncing of a well voltage. The bouncing of the well voltage is suppressed by reducing a resistance of the pocket p-type well PPWELL. A technique for reducing the resistance of the pocket p-type well PPWELL is a strapping technique. The strapping is to arrange metal lines over the pocket p-type well PPWELL in parallel and electrically contact the metal lines with the pocket p-well PPWELL. Such metal lines are named xe2x80x9cstrapping linesxe2x80x9d.
In the pocket p-type well PPWELL, as illustrated in FIG. 6, there exist coupling capacitors formed between the pocket p-type well PPWELL and bit lines BL and a resistance of the pocket p-type well PPWELL. Disposing the strapping lines with large conductivity over the pocket p-type well PPWELL can reduce the resistance of the pocket p-type well PPWELL. Referring to FIG. 7A which shows a relationship between a strapping line number and a well voltage, as the number of strapping lines increases, the bouncing of a well voltage is reduced more and more. Similarly, as the number of strapping lines increases, a discharge time of a bounced well voltage is shortened more and more. A simulation result in FIG. 7A is obtained using variables illustrated in FIG. 7B. As a result, as the number of strapping lines increases, the word line enable point of time is advanced or a delay time thereof is shortened. It means that a total program time is shortened.
However, in a case where the strapping lines are disposed too much, an array size is increased in proportion to the increased number of the strapping lines, so that the chip size is increased. Bouncing of a voltage of pocket p-type well due to charging of bit lines can be reduced somewhat by the strapping lines. But, a sufficient margin or time interval is still necessary between a bit line enable point of time and a word line enable point of time.
It is therefore an object of the invention to provide a nonvolatile semiconductor memory device capable of securing an optimum program time without program disturb due to bouncing of a substrate voltage and a method for programming the device.
It is another object of the invention to provide a nonvolatile semiconductor memory device capable of exactly forecasting a point of time when a bounced well voltage is stabilized.